projects

Latest Projects

  1. VLSI Implementation of Text to Image Encryption Algorithm based on Private Key encryption
  2. FPGA Implementation of Data Encryption Standard (DES) and its verification
  3. Design and Implimentation of 64-Bt MAC unit vedic multiplier and it’s verification using system verilog.
  4. Design and Verification of I2S bus Controller with APB interface
  5. Design and Modelling of I2C Communication Protocol.
  6. Implementation and verification of AXI to I2C interface.
  7. Implementation and verification of AHB to APB interface.
  8. Design of an efficient FSM for Implementation of AMBA AHB Master.
  9. Design and verification of SPI protocol & interfacing with LCD.
  10. Design and verification of DDR3 memory controller.
  11. Implementation and verification of systolic 8 bit multiplier.
  12. Implementation of Vedic multiplier based DSP system and verification.
  13. Design and Verification of AHB-Lite
  14. Design and Verification of SPI Bus Protocol with Built-In-Self-Test Capability
  15. Design, Verification and Implementation of USB 3.0 PHY Transmitter
  16. Design and Verification of i2c interface having single master and multiple slaves
  17. Design and Verification of AXI4 Lite Master and Slave
  18. Design and Verification of Communication bridge between I2C and SPI protocol
  19. Design and Verification of I2C Master compatible with Wishbone Interface
  20. Design and Verification of AXI4 LITE Master
  21. Design, Verification and Implementation of MODBUS RTU Protocol.
  22. Design and Implementation of AXI interconnect and AXI to APB bridge.
  23. Design and Verification of SPI to I2C Bridge and its FPGA Implementation.
  24. Implementation of AES encryption and decryption
  25. Design and verification of memory controller using AMBA AHB lite protocol
  26. Implementation and Verification of AHB-APB AMBA Bridge.
  27. Design and verification of transactions using AXI-4 Lite protocol.
  28. FPGA Implementation Of Floating Point Multiplier Using Urdhva-Tiryagbhyam
  29. Design And Verification Of 5 Stage 32 Bit RISC Processor

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